(a) Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same, and more particularly, to a composite semiconductor device having a high power element of a high withstand voltage and control circuit elements integrated in a monolithic structure and a method for fabricating the same.
(b) Description of the Related Art
In a conventional composite semiconductor device having a first circuit region for control circuit elements and a second circuit region for a power element integrated in a monolithic structure, in order to improve the current efficiency, the electrodes of the power element, for example, the source and gate electrodes of a power MOS FET are formed on a main surface of the substrate on which the control circuit elements are formed, and the drain electrode of the power MOS FET is formed on the back surface of the substrate. In this construction, the power element and the control circuit elements must be isolated from each other by an element isolation region.
A conventional method for fabricating a composite semiconductor device will be described below with reference to FIG. 1, which shows a cross-sectional view of the composite semiconductor device. The method is disclosed, for example, in IEEE Power Electronics Specialist Conference 88 Record, April, 1988, pp. 1325 to 1329, and in Japanese Patent Laid-Open Publication NO. 1990-168646. The semiconductor device has a bonded wafer including a first substrate having a high resistivity and a second substrate having a low resistivity.
A first n- epitaxial layer 22A is formed over the entire surface of an n.sup.+ -type silicon substrate (second substrate) 21. Then, a silicon oxide film 24 is formed on the surface of an n.sup.- -type silicon substrate (first substrate) 23. The n+ silicon substrate 21 and the n- silicon substrate 23 are bonded to each other by coupling the silicon oxide film 24 to the first epitaxial layer 22A after washing both the substrates and by a subsequent heat-treatment. Then, the surface of the n- silicon substrate 23, i.e., a main surface of the bonded wafer opposite to the surface on which the silicon oxide film 24 is formed is ground to obtain a predetermined thickness.
Subsequently, the first silicon substrate 23 and the silicon oxide film 24 are removed by an etching in a region 30, then a second n- epitaxial layer 22B is grown thereinto in a thickness equal to the total thickness of the substrate 23 and the silicon oxide films 24 to obtain the region 30 for forming the power element.
Next, an anisotropic etching is applied to the n- silicon substrate 23 at the main surface using a photoresist film as a mask thereby to form V-shaped trenches reaching the surface of the silicon oxide film 24, following which a thin silicon oxide film 7A is formed on the entire surface including the surfaces of the n- silicon substrate 23 and the second epitaxial layer 22B by a thermal oxidation. A laminated layer of a silicon nitride film and a BPSG film is then formed over the entire surface of the silicon oxide film 7A to provide a filling layer 8A. The laminated layer 8A is then ground to expose the silicon oxide film 7A, which is then removed by a wet-etching thereby to expose the surfaces of the n- silicon substrate 23 and the second epitaxial layer 22B and to leave the filling layers 8A.
Finally, a power element and control circuit elements composed of NPN transistors, CMOS FETs or the like are formed in the island regions of the monocrystalline silicon substrate 23 isolated by the silicon oxide film 24 and the filling layers 8A.
With the conventional method for fabricating a composite semiconductor device as described above, the second circuit region 30 for forming a power element is obtained by means of the growth of an epitaxial layer 22B, as a result of which an abnormal growth of polycrystalline silicon occurs at an interface as designated by a circle "A" between the silicon oxide film 24 and the second epitaxial layer 22B. Accordingly, the monocrystalline epitaxial layer 22B of the second circuit region 30 is distorted, and crystal defects such as dislocation and the like will occur. Besides, since the second epitaxial layer 22B is very thick, the epitaxial growth thereof costs a lot of time.
Thus, there arise problems that the yield and reliability of a composite semiconductor device are reduced and that the growth of the epitaxial layer raises the fabrication cost of the composite semiconductor device.